研究生日记

为什么时序逻辑需要滞后一个时钟周期

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FPGA 学习 & 实战
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研究生日记

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FPGA 学习 & 实战
FPGA 学习 & 实战
- 基础知识
  基础知识
  - 常用 IP 核
    常用 IP 核
    
    FFT IP 核使用方法
    
    RAM IP 核使用方法
    
    ROM IP 核使用方法
    
    自定义 IP 封装
  - 常用通信协议
    常用通信协议
    
    I2C 协议
    
    RS485 串口协议
    
    SPI 协议
    
    千兆以太网通信
    
    FPGA 实现 CAN 通信
    
    HDMI 显示器驱动设计
    
    差分对和差分信号
    
    VGA 显示器驱动设计
    
    VGA 显示器驱动 -- 字符游走
    
    基于 ROM 的 VGA 图像显示
  - DDR3
    DDR3
    
    01_AXI4 基础知识
    
    02_AXI4_Lite 的读写通道和仿真代码的实现
    
    DDR3 读写控制器的设计与验证
  - AD 外设
    AD 外设
    
    AD 外设的原理
    
    简易频率计的设计与验证
    
    数字示波器设计
  - 存储器
    存储器
    
    ROM、RAM、FIFO 知识点整理、区分、应用案例
  - 状态机
    状态机
    
    状态机相关知识
  - 时序设计
    时序设计
    
    时序约束
    
    为什么时序逻辑需要滞后一个时钟周期
  - 数字电路基础
    数字电路基础
    
    数字电路基础
  - ZYNQ 专题
    ZYNQ 专题
    
    ZYNQ 的介绍
  - 其他
    其他
    
    DHT11 温湿度显示
    
    并行数据转为串行数据
    
    电路的动态特性
    
    高速光通信项目
    
    高速接口的学习
    
    锁存器和触发器的理解与整理
    
    数码管动态显示
    
    笔试题目汇总
    
    使用 python 修改图像格式
    
    FPGA 与 CPLD 的区别与联系
    
    TestBench 编写技巧
    
    fpga 的 mt9v034 摄像头配置及 hdmi 显示输出
    
    为什么 FPGA 的阻塞赋值会延时一个时钟周期，而在某些情况下不延时一个时钟周期呐？
- 笔试题目练习
  笔试题目练习
  - 牛客网
    牛客网
    
    题目 59_根据 RTL 图编写 Verilog 程序
    
    题目 60_使用握手信号实现跨时钟域数据传输
    
    IIC 与 SCCB 协议的联系与区别
    
    面试实战
  - HDLBits 练习
    HDLBits 练习
    
    Getting Started
    Getting Started
    
    Getting Started
    
    Output Zero
    
    Verilog Language
    Verilog Language
    
    Basics
    Basics
    
    Simple wire
    
    Four wires
    
    Inverter
    
    AND gate
    
    NOR gate
    
    XNOR gate
    
    Declaring wires
    
    7458 chip
    
    Vectors
    Vectors
    
    Vectors
    
    Vectors in more detail
    
    Vector part select
    
    Bitwise operators
    
    Four input gates
    
    Vector concatenation operator
    
    Vector reversal 1
    
    Replication operator
    
    More replication
    
    Modules:Hierarchy
    Modules:Hierarchy
    
    Modules
    
    Connecting ports by position
    
    Connecting ports by name
    
    Three modules
    
    Modules and vectors
    
    Adder 1
    
    Adder 2
    
    Carry select adder
    
    Adder subtractor
    
    Procedures
    Procedures
    
    Always blocks (combinational)
    
    Always blocks (clocked)
    
    If statement
    
    If statement latches
    
    Case statement
    
    Priority encoder
    
    Priority encoder with casez
    
    Avoiding latches
    
    More Verilog Features
    More Verilog Features
    
    Conditional ternary operator
    
    Reduction operators
    
    Reduction Even wider gates
    
    Combinational for loop Vector reversal 2
    
    Combinational for loop 255 bit population count
    
    Generate for loop 100 bit binary adder 2
    
    Generate for loop 100 digit BCD adder
    
    Circuits
    Circuits
    
    Combinational_Logic
    Combinational_Logic
    
    Basic_Gates
    Basic_Gates
    
    Wire
    
    GND
    
    NOR
    
    Another gate
    
    Two gates
    
    More logic gates
    
    7420 chip
    
    Truth tables
    
    Two bit equality
    
    Simple circuit A
    
    Simple circuit B
    
    Combine circuits A and B
    
    Ring or vibrate
    
    Thermostat
    
    3 bit population count
    
    Gates and vectors
    
    Even longer vectors
    
    Multiplexers
    Multiplexers
    
    2 to 1 multiplexer
    
    2 to 1 bus multiplexer
    
    9 to 1 multiplexer
    
    256 to 1 multiplexer
    
    256 to 1 4 bit multiplexer
    
    Arithmetic_Circuits
    Arithmetic_Circuits
    
    Half adder
    
    Full adder
    
    3 bit binary adder
    
    Adder
    
    Signed addition overflow
    
    100 bit binary adder
    
    4 digit BCD adder
    
    Karnaugh_Map_to_Circuit
    Karnaugh_Map_to_Circuit
    
    3-variable
    
    4-variable
    
    4-variable(1)
    
    4-variable(2)
    
    Minimum_SOP_and_POS
    
    Karnaugh_map
    
    Karnaugh_map(1)
    
    K-map_implemented_with_a_multiplexer
    
    Sequential_Logic
    Sequential_Logic
    
    Latches_and_Flip-Flops
    Latches_and_Flip-Flops
    
    D_flip-flop
    
    D_flip-flops
    
    DFF_with_reset
    
    DFF_with_reset_value
    
    DFF_with_asynchronous_reset
    
    DFF_with_byte_enable
    
    D_Latch
    
    DFF(1)
    
    DFF(2)
    
    DFF+gate
    
    Mux_and_DFF
    
    Mux_and_DFF(1)
    
    DFFs_and_gates
    
    Create_circuit_from_truth_table
    
    Detect_an_edge
    
    Detect_both_edges
    
    Edge_capture_register
    
    Dual-edge_triggered_flip-flop
    
    Counters
    Counters
    
    Four-bit_binary_counter
    
    Decade_counter
    
    Decade_counter_again
    
    Slow_decade_counter
    
    Counter_1-12
    
    Counter_1000
    
    4-digit_decimal_counter
    
    12-hour_clock
    
    Shift_Registers
    Shift_Registers
    
    4-bit_shift_register
    
    Left-right_rotator
    
    Left-right_arithmetic_shift
    
    5-bit_LFSR
    
    3-bit_LFSR
    
    32-bit_LFSR
    
    Shift_register(1)
    
    Shift_register(2)
    
    3-input_LUT
    
    More_Circuits
    More_Circuits
    
    Rule_90
    
    Rule_110
    
    Conways_Game_of_Life_16x16
    
    Finite_State_Machines
    Finite_State_Machines
    
    Simple_FSM_1_async
    
    Simple_FSM_1_sync
    
    Simple_FSM_2_async
    
    Simple_FSM_2_sync
    
    Simple_state_transitions_3
    
    Simple_one-hot_state_transitions_3
    
    Simple_FSM_3_async
    
    Simple_FSM_3_sync
    
    Design_a_Moore_FSM
    
    Lemmings_1
    
    Lemmings_2
    
    Lemmings_3
    
    Lemmings_4
    
    One-hot_FSM
    
    PS2_packet_parser
    
    PS2_packet_parser_and_datapath
    
    Serial_receiver
    
    Serial_receiver_and_datapath
    
    Serial_receiver_with_parity_checking
    
    Sequence_recognition
    
    Design_a_Mealy_FSM
    
    Serial_twos_complementer_Moore
    
    Serial_twos_complementer_Mealy
    
    FSM(1)
    
    FSM(2)
    
    FSM_logic
    
    FSM_next-state_logic
    
    FSM_one-hot_next-state_logic
    
    FSM(3)
    
    FSM(4)
    
    One-hot_FSM_equations
    
    FSM(5)
    
    Another_FSM
    
    Building_Larger_Circuits
    Building_Larger_Circuits
    
    Counter_with_period_1000
    
    4-bit_shift_register_and_down_counter
    
    FSM_Sequence_1101_recognizer
    
    FSM_Enable_shift_register
    
    FSM_The_complete_FSM
    
    The_complete_timer
    
    FSM_One-hot_logic_equations
    
    Verification_Reading Simulations
    Verification_Reading Simulations
    
    Mux
    
    NAND
    
    Mux(1)
    
    Add_sub
    
    Case_statement
    
    Combinational_circuit1
    
    Combinational_circuit2
    
    Combinational_circuit3
    
    Combinational_circuit4
    
    Combinational_circuit5
    
    Combinational_circuit6
    
    Sequential_circuit7
    
    Sequential_circuit8
    
    Sequential_circuit9
    
    Sequential_circuit10
    
    Verification:Writing Testbenches
    Verification:Writing Testbenches
    
    AND gate
    
    Clock
    
    T flip flop
    
    Testbench1
    
    Testbench2
    
    Cs450
    
    Cs450
原理图 & PCB 设计
原理图 & PCB 设计
- 基础知识
  基础知识
  - 元器件
    元器件
    
    电阻

为什么时序逻辑需要滞后一个时钟周期

开发中・・・为什么时序逻辑需要滞后一个时钟周期.md

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