数码管动态显示
演示视频，下载下来观看 download:https://cdn.jsdmirror.com/gh/zikwq/Blog_Pic/e8e08759159b97eaaae26cac1a17c68e.mp4
```verilog seg.v module top( clk, //系统输入时钟
rst_n,//系统复位
segdata,//数码管段选
segcs//数码管位选
);
input clk; input rst_n;
output reg [7:0]segdata; output reg [2:0]segcs;
reg[31:0] count; reg[24:0]count1ms;
reg[2:0]number;
reg[19:0]tenvalue; reg clk1ms;
parameter sample=2'b00, display=2'b01;
//-----------数码管驱动时钟----------- always@(posedge clk) begin if(count1ms>25'd1000_0) begin clk1ms<=~clk1ms; count1ms<=0; end else count1ms<=count1ms+1; end
//-----------从0开始显示数字----------- always@(posedge clk1ms or negedge rst_n) if(!rst_n) tenvalue <= 20'd0; else if(tenvalue == 20'd999999) tenvalue <= 20'd0; else tenvalue <= tenvalue + 1'd1;
//-----------数码管译码----------- function[7:0] leddata; input[3:0] datain; begin case(datain) 4'd0: leddata=8'b11000000;//0 4'd1: leddata=8'b11111001;//1 4'd2: leddata=8'b10100100;//2 4'd3: leddata=8'b10110000;//3 4'd4: leddata=8'b10011001;//4 4'd5: leddata=8'b10010010;//5 4'd6: leddata=8'b10000010;//6 4'd7: leddata=8'b11111000;//7 4'd8: leddata=8'b10000000;//8 4'd9: leddata=8'b10010000;//9 4'd10: leddata=8'b10111111;//- 4'd11: leddata=8'b01111111;//. default:leddata=8'bzzzz_zzzz; endcase end endfunction
//-----------数码管扫描-----------
always@(posedge clk1ms)
begin
if(number==3'd6) number<=0;
else
begin
number<=number+1;
case(number)
4'd0:
begin
segdata<=leddata((tenvalue/10)%10);//个位
segcs<=3'b101;
end
4'd1:
begin
segdata<=leddata((tenvalue/100)%10);//十位
segcs<=3'b100;
end
4'd2:
begin
segdata<=leddata((tenvalue/1000)%10); //百位
segcs<=3'b011;
end
4'd3:
begin
segdata<=leddata((tenvalue/10000)%10);//千位
segcs<=3'b010;
end
4'd4:
begin
segdata<=leddata((tenvalue/100000)%10);//万位
segcs<=3'b001;
end
4'd5:
begin
segdata<=leddata((tenvalue/1000000)%10);//十万位
segcs<=3'b000;
end
endcase
end
end
endmodule
```
