Declaring wires

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
wire a_b;
wire c_d;
wire b_d;
assign a_b = a&b;
assign c_d = c&d;
assign b_d = a_b|c_d;
assign out = b_d;
assign out_n = ~b_d;

endmodule